Execution unit

ABSTRACT

An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent application Ser. No. 16/428,901, filed on May 31, 2019, which claims priority to United Kingdom Patent Application No. 1903346.3, filed on Mar. 11, 2019, the disclosures of which are hereby incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to an execution unit of a processor. The disclosure relates particularly to an execution unit configured to evaluate functions using at least one multiplier circuit.

BACKGROUND

In computing, bit sequences of predefined sizes are used to represent numbers. The particular representation of the bit sequence determines how a bit sequence is interpreted.

One form of representation is the floating-point representation, which is often used to approximately represent real numbers. The floating-point representation comprises 3 separate components, i.e. a sign component, a mantissa component, and an exponent component. In the single-precision (i.e. 32-bit) floating point representation according to the IEEE 754 standard, the sign component consists of a single bit, the exponent consists of 8 bits, and the mantissa consists of 23 bits. In the half-precision (i.e. 16-bit) floating-point representation, the sign component consists of a single bit, the mantissa consists of 10 bits, and the exponent consists of 5 bits. In most cases, a number is given from these 3 components by the following formula: (−1)^(signbit) ×I·mantissa×2^(exponentbits-offset)

The “offset” to the exponent is dependent upon the number of bits used to represent the exponent, which is dependent upon the precision level. In the single-precision representation, the offset is equal to 127. In the half-precision format, the offset is equal to 15.

Here “I” is an implicit bit, which is derived from the exponent. In the case that the exponent bit sequence consists of anything other than all zeros or all ones, the implicit bit is equal to one and the number is known as a “Norm”. In this case, the floating point number is given by: (−1)^(signbit)×1·mantissa×2^(exponentbits-offset)

In the case that the exponent bit sequence consists of all zeros, the implicit bit is equal to zero and the number is known as a “denorm”. In this case, the floating point number is given by: (−1)^(signbit)×0·mantissa×2^(exponentbits-offset)

The denorms are useful, since they allow smaller numbers to be represented than would otherwise be representable by the limited number of exponent bits.

The other circumstance—in which the exponent bit sequence consists of all ones—may be used to represent special cases, e.g. ±infinity or NaN (not a number). NaN is a numeric data type value representing an undefined or unrepresentable value. The presence of a NaN in the results of a calculation is often taken to signal an exception.

Another form of representation is the integer representation. The integer may be signed, in which case a single bit of the bit sequence is used to represent the sign of the number, with the remaining bits of the bit sequence used to represent the magnitude of the number. Alternatively, the integer may be unsigned, in which case all of the bits of the bit sequence are used to represent the magnitude of the number.

The floating point representation may be used to represent numbers in implementations of neural network processing. An implementation of neural networks involves the storage and manipulation of such floating point numbers. Neural networks are used in the field of machine learning and artificial intelligence. Neural networks comprise arrangements of sets of nodes which are interconnected by links and which interact with each other. The principles of neural networks in computing are based on information about how electrical stimuli convey information in the human brain. For this reason, the nodes are often referred to as neurons. They may also be referred to as vertices. The links are sometimes referred to as edges. The network can take input data and certain nodes of the network can perform operations on the data. The results of these operations are passed to other nodes. The output of each node is referred to as its activation or node value. Each link is associated with a weight. A weight defines the connectivity between nodes of the neural network. Many different techniques are known by which neural networks are capable of learning. The learning takes place by altering values of the weights.

FIG. 1 shows an extremely simplified version of one arrangement of nodes in a neural network. This type of arrangement is often used in learning or training and comprises an input layer of nodes, a hidden layer of nodes and an output layer of nodes. In reality, there will be many nodes in each layer, and nowadays there may be more than one layer per section. Each node of the input layer Ni is capable of producing at its output an activation or node value which is generated by carrying out a function on data provided to that node. A vector of node values from the input layer is scaled by a vector of respective weights at the input of each node in the hidden layer, each weight defining the connectivity of that particular node with its connected node in the hidden layer. In practice, networks may have millions of nodes and be connected multi-dimensionally, so the vector is more often a tensor. The weights applied at the inputs of the node Nh are labelled w0 . . . w2. Each node in the input layer is connected at least initially to each node in the hidden layer. Each node in the hidden layer can perform an activation function on the data which is provided to them and can generate similarly an output vector which is supplied to each of the nodes N₀ in the output layer N₀. Each node weights its incoming data, for example by carrying out the dot product of the input activations of the node and its unique weights for the respective incoming links. It then performs an activation function on the weighted data. The activation function can be for example a sigmoid. See FIG. 1A. The network learns by operating on data input at the input layer, assigning weights to the activations from each node and acting on the data input to each node in the hidden layer (by weighting it and performing the activation function). Thus, the nodes in the hidden layer operate on the weighted data and supply outputs to the nodes in the output layer. Nodes of the output layer may also assign weights. Each weight is characterised by a respective error value. Moreover, each node may be associated with an error condition. The error condition at each node gives a measure of whether the error in the weight of the node falls below a certain level or degree of acceptability. There are different learning approaches, but in each case there is a forward propagation through the network from left to right in FIG. 1 , a calculation of overall error, and a backward propagation from right to left in FIG. 1 through the network of the error. In the next cycle, each node takes into account the back-propagated error and produces a revised set of weights. In this way, the network can be trained to perform its desired operation.

Certain well known functions, such as divide, exponential, logarithm and square root, may have applications in neural network processing. A problem with which this present application is concerned is how to provide a suitable execution unit configured to generate values for such functions quickly and accurately, and preferably in a manner which optimises the use of processing resources.

SUMMARY

According to a first aspect, there is provided an execution unit for a processor, the execution unit comprising a hardware module comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions of input values, wherein the processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result, the processing pipeline comprising a plurality of processing circuits, each configured to perform an operation on one or more values to provide a result during at least one stage of the plurality of stages, wherein the plurality of processing circuits comprises a plurality of multiplier circuits, each configured to multiply together two or more values to produce a multiplication result during at least one stage of the plurality of stages, wherein the plurality of multiplier circuits comprises a first multiplier circuit and a second multiplier circuit that are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform processing of one or more values, wherein the plurality of multiplier circuits comprises a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, wherein the third multiplier circuit is configured to process outputs from the first multiplier circuit and the second multiplier circuit.

In some embodiments, the hardware module comprises control circuitry configured to control which values are provided to each of the plurality of processing circuits, wherein the execution unit is configured to: execute an instruction comprising an op code indicating a first mathematical function of the plurality of mathematical functions; access an operand defined by the instruction; in response to the execution of the instruction, provide a first at least one input value dependent upon the operand to the processing pipeline; and provide control information associated with the instruction to the control circuitry to cause the control circuitry to control the supply of values to the plurality of processing circuits so as to cause the processing pipeline to evaluate the first mathematical function with respect to the operand.

In some embodiments, the first at least one input value comprises the operand.

In some embodiments, the processing pipeline is configured to, when evaluating a mathematical function, for each of the plurality of stages, assign a time slot of a plurality of time slots for performing processing associated with the respective stage for evaluating the mathematical function.

In some embodiments, at least one of the plurality of multiplier circuits is configured to: perform processing associated with a first mathematical function during a first of the time slots; and perform processing associated with a second mathematical function during a second of the time slots immediately following the first of the time slots.

In some embodiments, the control circuitry is configured to, following the start of the first of the time slots, re-configure the supply of values to the at least one of the plurality of multiplier circuits so as to enable the at least one of the plurality of multiplier circuits to perform processing associated with the second mathematical function during the second of the time slots.

In some embodiments, at least one of the first multiplier circuit and the second multiplier circuit is configured to, at a first time, perform processing associated with a first mathematical function, wherein the third multiplier circuit is configured to, at the first time, perform processing associated with a second mathematical function different to the first mathematical function.

In some embodiments, the control circuitry comprises a plurality of multiplexers of the processing pipeline configured to control which values are provided to each of the plurality of processing circuits.

In some embodiments, the outputs of the first multiplier circuit and the second multiplier circuit are modified by further processing circuitry of the plurality of processing circuits prior to being provided to the third multiplier circuit for processing.

In some embodiments, the plurality of processing circuits comprise one or more of: at least one addition circuit configured to receive two or more values and determine an addition result; at least one subtraction circuit configured to receive two or more values and determine a subtraction result; and a circuit configured to search a look up table in dependence upon one or more values and output a result from the look up table.

In some embodiments, the plurality of mathematical functions comprise at least one of: an exponential function; a divide function; a square root function; and a logarithm function.

In some embodiments, when evaluating one of the mathematical functions, the execution unit is configured to: supply one or more input values to the processing pipeline; process, in the pipeline, the received one or more input values to produce one or more output values; supply at least one of the one or more output values as at least one input to a start of the processing pipeline; and process, in the pipeline, the received at least one of the one or more output values to produce a result for the one of the mathematical functions.

According to a second aspect, there is provided a method of operating an execution unit in a processor execution unit comprising a hardware module comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions of input values, wherein the processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result, the method comprising: performing, at each of a plurality of processing circuits in the processing pipeline, an operation on one or more values to provide a result during at least one stage of the plurality of stages; multiplying together, at each of a plurality of multiplier circuits of the plurality of processing circuits, two or more values to produce a multiplication result during at least one stage of the plurality of stages; operating, a first of the plurality of multiplier circuits and a second of the plurality of multiplier circuits, in parallel such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform processing of one or more values; and processing, at a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, outputs from the first multiplier circuit and the second multiplier circuit.

In some embodiments, the hardware module comprises control circuitry configured to control which values are provided to each of the plurality of processing circuits, wherein the method comprises: executing an instruction comprising an op code indicating a first mathematical function of the plurality of mathematical functions; accessing an operand defined by the instruction; in response to the execution of the instruction, providing a first at least one input value dependent upon the operand to the processing pipeline; and providing control information associated with the instruction to the control circuitry to cause the control circuitry to control the supply of values to the plurality of processing circuits so as to cause the processing pipeline to evaluate the first mathematical function with respect to the operand.

In some embodiments, the first at least one input value comprises the operand.

In some embodiments, the method comprises: when evaluating a mathematical function, for each of the plurality of stages, assigning a time slot of a plurality of time slots for performing processing associated with the respective stage for evaluating the mathematical function.

In some embodiments, the method comprises: at least one of the plurality of multiplier circuits performing processing associated with a first mathematical function during a first of the time slots; and the least one of the plurality of multiplier circuits performing processing associated with a second mathematical function during a second of the time slots immediately following the first of the time slots.

In some embodiments, the method comprises: following the start of the first of the time slots, re-configuring the supply of values to the at least one of the plurality of multiplier circuits so as to enable the at least one of the plurality of multiplier circuits to perform processing associated with the second mathematical function during the second of the time slots.

In some embodiments, the method comprises: at a first time, at least one of the first multiplier circuit and the second multiplier circuit performing processing associated with a first mathematical function; and, at the first time, the third multiplier circuit performing processing associated with a second mathematical function different to the first mathematical function.

In some embodiments, the control circuitry comprises a plurality of multiplexers of the processing pipeline configured to control which values are provided to each of the plurality of processing circuits.

In some embodiments, the method comprises modifying by further processing circuitry of the plurality of processing circuits, the outputs of the first multiplier circuit and the second multiplier circuit prior to them being provided to the third multiplier circuit for processing.

In some embodiments, the method comprises: receiving two or more values and determining an addition result from the two or more values; receiving two or more values and determining a subtraction result from the two or more values; and searching a look up table in dependence upon one or more values and outputting a result from the look up table.

In some embodiments, the plurality of mathematical functions comprise at least one of: an exponential function; a divide function; a square root function; and a logarithm function.

In some embodiments, the method comprises: when evaluating one of the mathematical functions, supplying one or more input values to the processing pipeline; processing, in the pipeline, the received one or more input values to produce one or more output values; supplying at least one of the one or more output values as at least one input to a start of the processing pipeline; and processing, in the pipeline, the received at least one of the one or more output values to produce a result for the one of the mathematical functions.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments will now be described by way of example only with reference to the accompanying figures in which:

FIG. 1 is a highly simplified schematic view of a neural net;

FIG. 1A is highly simplified schematic view of a neuron;

FIG. 2 schematically illustrates an arrangement for exchanging data between tiles;

FIG. 3 illustrates a processing pipeline for evaluating functions;

FIG. 4 illustrates a number line of floating point numbers;

FIG. 5 a illustrates the first two traversals of the processing pipeline for calculating a divide;

FIG. 5 b illustrates the final two traversals of the processing pipeline for calculating a divide;

FIG. 6 a illustrates the first two traversals of the processing pipeline for calculating a square root;

FIG. 6 b illustrates the next two traversals of the processing pipeline for calculating a square root;

FIG. 6 c illustrates the final traversal of the processing pipeline for calculating a square root;

FIG. 7 a illustrates the first two traversals of the processing pipeline for calculating a logarithm;

FIG. 7 b illustrates the next two traversals of the processing pipeline for calculating a logarithm,

FIG. 7 c illustrates the final two traversals of the processing pipeline for calculating a logarithm;

FIG. 8 illustrates the division of a power function into different components;

FIGS. 9 a and 9 b illustrate the evaluation of different components of a power function;

FIG. 10 illustrates the first three traversals of the processing pipeline for calculating an exponential function;

FIG. 11 illustrates the final two traversals of the processing pipeline for calculating an exponential function; and

FIG. 12 is a schematic diagram illustrating a processor having an execution unit for evaluating a plurality of mathematical functions.

DETAILED DESCRIPTION

The present disclosure concerns an execution unit configured to evaluate functions. The unit comprises a plurality of multipliers that are interconnectable to efficiently operate in a pipelined manner. The following description explains various embodiments of the application in further detail. The techniques described herein can be used with the intelligence processing units (IPUs) described in our earlier U.S. application Ser. No. 15/885,925, the contents of which are herein incorporated by reference. Such an IPU comprises a plurality of tiles (only one of which is shown herein) interconnected by a switching fabric to form a chip. Such chips can be connected together using links on the chip to form a multi-chip processor.

FIG. 2 illustrates an example tile 4 in accordance with embodiments of the present disclosure. In the tile 4, multiple threads are interleaved through a single execution pipeline. Data is received at the tile via an exin interface 224, and transmitted from the tile via an exout interface 226. The tile 4 comprises: a plurality of contexts 26 each arranged to represent the state of a different respective one of a plurality of threads; a shared instruction memory 12 common to the plurality of threads; a shared data memory 22 that is also common to the plurality of threads; a shared execution pipeline 14, 16, 18 that is again common to the plurality of threads; and a thread scheduler 24 for scheduling the plurality of threads for execution through the shared pipeline in an interleaved manner. The thread scheduler 24 is schematically represented in the diagram by a sequence of time periods S₀ . . . S₅, but in practice is a hardware mechanism for managing program counters of the threads in relation to their time periods. The execution pipeline comprises a fetch stage 14, a decode stage 16, and an execution stage 18 comprising an execution unit (EXU) and a load/store unit (LSU). Each of the contexts 26 comprises a respective set of registers R₀, R₁ . . . for representing the program state of the respective thread.

The fetch stage 14 is configured to fetch instructions to be executed from the instruction memory 12, under control of the thread scheduler 24. The thread scheduler 24 is configured to control the fetch stage 14 to fetch instructions from the local program for execution in each time period as will be discussed in more detail below.

The fetch stage 14 has access to a program counter (PC) of each of the threads that is currently allocated to a time period. For a given thread, the fetch stage 14 fetches the next instruction of that thread from the next address in the instruction memory 12 as indicated by the thread's program counter. Note that an instruction, as referred to herein, means a machine code instruction, i.e. an instance of one of the fundamental instructions of the computer's instruction set, made up of an opcode and zero or more operands. Note too that the program loaded into each tile is determined by a processor or compiler to allocate work based on the graph of the machine intelligence model being supported. Note that the operand may be given in an operand field in the instruction, or may be accessed by a memory address or register identifier at which the operand is stored. In a further example, the operand may be implicitly defined by the instructions (for example held in an implicitly defined register).

The fetch stage 14 then passes the fetched instruction to the decode stage 16 to be decoded, and the decode stage 16 then passes an indication of the decoded instruction to the execution stage 18 along with the decoded addresses of any operand registers of the current context specified in the instruction, in order for the instruction to be executed.

In the present example, the thread scheduler 24 interleaves threads according to a round-robin scheme whereby, within each round of the scheme, the round is divided into a sequence of time periods S₀, S₁, S₂, S₃, each for executing a respective thread. Typically each slot is one processor cycle long and the different slots are evenly sized (though not necessarily so in all possible embodiments). This pattern then repeats, each round comprising a respective instance of each of the time periods (in embodiments in the same order each time, though again not necessarily so in all possible embodiments). Note therefore that a time period in this context means the repeating allocated place in the sequence, not a particular instance of the time period in a given repetition of the sequence. In the illustrated embodiment, there are eight time periods, but other numbers are possible. Each time period is associated with a hardware resource, e.g. a register, for managing the context of an executing thread.

One of the contexts 26, labelled SV, is reserved for a special function, to represent the state of a “supervisor” (SV) whose job it is to coordinate the execution of “worker” threads. The supervisor can be implemented as a program organised as one or more supervisor threads which may run concurrently.

Each worker thread is a codelet intended to represent a vertex in the graph and to execute atomically. That is all the data it consumes is available at launch and all the data it produces is not visible to other threads until it exits. It runs to completion (excepting error conditions).

During execution, the worker threads may require different types of functions, such as divides and square roots, to be evaluated. One known algorithm that is frequently used to evaluate hyperbolic and trigonometric functions is the CORDIC algorithm. The CORDIC algorithm utilises a series of shift and add operations to determine values for functions. Such shift and add algorithms may be applied to evaluate logarithms, exponentials, divides and square roots. The shift and add operations may be implemented in an execution module which comprises shifters and adders.

One of the disadvantages of the use of such shift and add circuits can be the linear convergence provided by such circuits. For example, CORDIC converges linearly to the value of a function by determining a set number of bits of the result every iteration. This may require a larger number of iterations in the case that the precision level of the numerical values is high.

Embodiments of the application address one or more of these issues by providing an execution unit as a hardware module comprising a processing pipeline having at least one multiplier circuit along with additional processing circuitry, such as addition and subtraction circuits. Multipliers and the additional processing circuitry of the processing pipeline may be used in different configurations to perform multiplications so as to evaluate different functions. The processing pipeline comprises a plurality of state elements placed between the multipliers, to store state values at the input of each pipeline stage. The state elements are in some cases associated with multiplexers to alter the connections between pipeline stages. The hardware module comprises control circuitry that is configured to control the multiplexers so as to determine the function evaluated using the processing pipeline. The hardware module may be used in conjunction with innovative function evaluation techniques to carry out a number of different functions in a single structure.

The pipeline comprises multipliers arranged such that a first multiplier and a second multiplier are configured to perform their operations in parallel at the same stage in the processing pipeline. A third multiplier is arranged in series with the first and second multiplier and process values dependent upon the outputs of the first and second multipliers. This enables the pipeline to perform parts of the calculation of a mathematical function in parallel and then to provide results of the parallel processing to later stages of the pipeline for further processing. Hence, the arrangement of multipliers in the pipeline advantageously improves the flexibility of the pipeline to be applied to evaluate different functions using the control circuitry.

Reference is made to FIG. 3 , which illustrates an example of a processing pipeline 300 according to examples of the application. As shown, the pipeline is divided into a plurality of stages E₀ . . . E₅.

The processing pipeline 300 comprises a plurality of multipliers 320 a, 320 b, 320 c, each of which is configured to multiply together two input values and to provide an output value. Each of the multipliers in this example carries out its respective processing over two stages of the processing pipeline. For example, multipliers 320 a and 320 b perform their processing during stages E₀ and E₁ of the processing pipeline 300. Therefore, these multipliers 320 a and 320 b operate in parallel. Multiplier 320 c, on the other hand, performs its processing during stages E₃ and E₄ of the pipeline. Multiplier 320 c, therefore, operates in series with the other two multipliers 320 a, 320 b.

The pipeline 300 may also contain additional processing circuitry 340 a, 340 b, and 340 c. This additional processing circuitry may be applied to perform a number of different operations, such as shifts and adds, on the results from the multipliers. The results of the first multiplier 320 a may be processed by additional processing circuitry 340 a. The results of the second multiplier 320 b may be processed by additional processing circuitry 340 b. The result of the third multiplier 320 c may be processed by additional processing circuitry 340 c.

The pipeline 300 comprises a plurality of state elements, such as flip-flops, (collectively referenced as 310) separating the stages of processing. The state elements are in some cases associated with multiplexers which control where the values resulting from each stage of processing are directed to during the next stage. The hardware module comprises control circuitry 330 for controlling the multiplexers. By controlling the multiplexers, the control circuitry 330 is used to select a function to be calculated by the processing pipeline. A plurality of different types of functions may be evaluated using the processing pipeline 300 by controlling where the outputs at each stages are directed during the next stage. For example, input multiplexers at state element 310 a are able to direct one or more received values such that they bypass the multiplier 320 a during the stages E₀ and E₁ or such that they are delivered to the multiplier 320 a for processing during the stages E₀ and E₁. Similarly, the multiplexer at input state element 310 b is able to direct one or more received values such that they bypass the additional processing circuitry 340 a during the stage E₂ or such that they are processed by the additional processing circuitry 340 a during the stage E₂. The additional processing circuitry 340 a may be capable of performing several different types of operation—e.g. addition, subtraction, shift, etc—on input values it receives. The multiplexor at state element 310 b may be configured to direct the values to specific inputs of the additional processing circuitry 340 a so as to cause a selected operation—e.g. addition, subtraction, shift, etc—to be performed by the additional processing circuitry 340 a.

The control circuitry 330 is configured, in response to the execution of an instruction by the execution unit, to control to which components the input values of the pipeline are directed. For example, the control circuitry 330 is configured to implement a divide operation in the pipeline 300 in response to the execution of a divide instruction by the execution unit. The input variable/s for such a function are provided as operands of the instruction. When the instruction is executed, due to a transport delay in providing the variables to the pipeline 300, the variables may be introduced into the pipeline following the first stage E₀. The variables may be received at state element 310 c, for example, bypassing the state element 310 a and multiplier 320 a. Similarly due to the transport delay, the result from the pipeline 300 may exit the pipeline 300 during the second to last stage E₄. The results that exit the pipeline 300 are returned to the worker thread that executed the instruction.

When variables that are being processed by the pipeline 300 reach the end of the pipeline 300, but the evaluation of the function is not yet complete, those variables are re-inserted into the pipeline at the first stage for another traversal of the pipeline. In this case, since variables are not returned to the worker thread that issued in the instruction, the hardware module comprising the pipeline indicates to the worker thread that the variables will not be returned and that another traversal of the pipeline is required.

When evaluating a mathematical function using the processing pipeline 300, the processing performed during each of the stages for that function may be performed during an allocated time slot. Each of the processing circuits in the pipeline 300 performs its processing during the time slot allocated for that processing. A single traversal of the pipeline 300 therefore takes 6 times slots to complete, since there are 6 stages. The processing performed by the multiplier 320 a takes places over two stages (E₀ and E₁). For a traversal of the pipeline by at least one value, a time slot is allocated for any processing during stage E₀ and a separate time slot is allocated for any processing during stage E₁. The multiplier 320 a is therefore configured to (if it has any processing to perform) perform its processing during the time slots allocated for stages E₀ and E₁. Similarly, a time slot is allocated for any processing during stage E₂ and the additional circuitry 340 a is configured to (if it has any processing to perform) perform its processing during the time slot allocated for stage E₂.

The processing pipeline 300 is configured to simultaneously evaluate a plurality of mathematical functions. During a single time slot, two or more of the plurality of stages in the pipeline 300 may be performing processing associated with different functions. For example, the multiplier 320 b may perform some of the processing for evaluating a first mathematical function (e.g. a logarithm) during a first time slot. Also during the first time slot, the multiplier 320 c may perform some of the processing for evaluating a second mathematical function (e.g. a divide).

Each of the components in the pipeline 300 may be configured to perform processing associated with different mathematical functions in different time slots. For example, during a first time slot, the additional circuitry 340 b may be configured to perform part of the processing for evaluating a first mathematical function (e.g. a square root). Then, during a second time slot following the first time slot, the additional circuitry may be configured to perform part of the processing for evaluating a second mathematical function (e.g. an exponential). Between the start of the first time slot and the start of the second time slot, the control circuitry 330 is configured to perform any necessary re-configuration of the relevant multiplexor/s to ensure that the correct input values are delivered to the correct inputs of the additional processing circuitry 340 b such that the additional processing circuitry performs the relevant processing for the second mathematical function during the second time slot.

By selecting the appropriate operations to be applied to input variables, the processing pipeline 300 may be applied to implement logarithm, exponential, divide, or square root functions. For some of these functions, the processing pipeline may implement a Newton-Raphson method as part of the evaluation of a function.

The Newton Raphson method is a method for successively finding better approximations for roots of a function. Circuitry based on Newton Raphson using multipliers may be implemented to evaluate functions, such as divide and square root functions. The Newton Raphson formula for determining iterations may be derived from a Taylor expansion of function f near x:

$\begin{matrix} {{f\left( {x + h} \right)} = {{f(x)} + {h\;{f^{\prime}(x)}} + {\frac{h^{2}}{2}{f^{''}(x)}} + \ldots}} & {{Eqn}\mspace{14mu} 1} \end{matrix}$

In many cases, terms higher than ƒ′(x) can be ignored. Then, h can be determined as:

$\begin{matrix} {h = {- \frac{f(x)}{f^{\prime}(x)}}} & {{Eqn}\mspace{14mu} 2} \end{matrix}$

Applying Eqn 2 allows the roots of the function to be iteratively derived. The Newton-Raphson method starts out with an initial guess x₀ for a root of the function f, and iteratively determines better approximations of the root. Using the initial guess x₀, a better approximation, x₁, is given by:

$\begin{matrix} {x_{1} = {{x_{0} + h} = {x_{0} - \frac{f\left( x_{0} \right)}{f^{\prime}\left( x_{0} \right)}}}} & {{Eqn}\mspace{14mu} 3} \end{matrix}$

The process is repeated to find better approximations by applying:

$\begin{matrix} {x_{n + 1} = {x_{n} - \frac{f\left( x_{n} \right)}{f^{\prime}\left( x_{n} \right)}}} & {{Eqn}\mspace{14mu} 4} \end{matrix}$

Eqn 4 is known as a first order Newton-Raphson, since it is derived by ignoring all of the terms higher than the first derivative (ƒ′(x)) in the Taylor expansion given by Eqn 1. If instead of ignoring all of the terms higher than the first derivative in Eqn 1, all of the terms higher than the second derivative (ƒ″(x)) are ignored, then the second order Newton Raphson may be derived from the Taylor expansion:

$\begin{matrix} {x_{n + 1} = {x_{n} - {\frac{f\left( x_{n} \right)}{f^{\prime}\left( x_{n} \right)}\left( {1 + \frac{2{f\left( x_{n} \right)}{f^{\prime}\left( x_{n} \right)}}{2{f^{\prime}\left( x_{n} \right)}^{2}}} \right)}}} & {{Eqn}\mspace{14mu} 5} \end{matrix}$

The first order Newton Raphson has the advantage that each iteration requires the use of fewer processing resources (e.g. multiplication and addition circuits) and less time to evaluate. The second order Newton Raphson has the advantage that each iteration produces a greater increase in accuracy.

As noted above, the CORDIC method for evaluating functions converges linearly and produces a set number of bits per iteration. Therefore, if initially only one bit of the answer is known, following each iteration in a CORDIC implementation, the known number of bits may increase as 1, 1+b, 1+2b, 1+3b . . . where b is the fixed number of bits produced per iteration. This method may require an undesirably high number of iterations, especially in the case that the required precision level of the result is high.

In contrast to the CORDIC method, the Newton Raphson Method instead produces increases in accuracy by a given factor in dependence upon the order used. If initially only one bit of the answer is known, following each iteration using a Newton Raphson of order n, the known number of bits increases as 1, (n+1)¹, (n+1)² . . . . For example, if a Newton Raphson of 1^(st) order is applied, the number of known bits doubles with each iteration: 1, 2, 4 . . . . In another example, if a Newton Raphson of 2^(nd) order is applied, the number of known bits triples with each iteration: 1, 3, 9 . . . . If a Newton Raphson of 3^(rd) order is applied, the number of known bits quadruples with each iteration: 1, 4, 16 . . . .

Therefore, it can be seen that with a second order Newton Raphson, an error reduction by a factor of 3 may achieved in only one iteration.

It is noted, however, that due to the scaling nature of Newton Raphson, the initial iteration produces relatively few known bits in comparison with later iterations. Therefore, in embodiments of the present application, a look up table is implemented to look up values for initial estimates, prior to applying the Newton Raphson method to improve upon the accuracy of the initial estimate. In this way, the number of Newton-Raphson iterations required to estimate a value for a function may be reduced.

The Newton Raphson method for determining the roots of functions may be applied to evaluate a plurality of commonplace functions. A look up table is combined to determine an initial value of a variable that is to be estimated using a circuit implementing the Newton Raphson method.

According to embodiments of the application, the hardware module is provided with at least one look up table. To evaluate a function of an operand, the look up table is searched using an index determined from the at least one operand to determine an initial estimate for the function. The hardware module comprises multiplication and addition/subtraction circuitry used to perform one or more Newton Raphson iterations, so as to improve the accuracy of the estimate derived from the look up table.

Once the Estimate for the value of the function based upon one or more Newton-Raphson iterations has been obtained, the hardware module is configured to perform a rounding operation so as to place the result in the floating point format. For example, the single-precision floating point format has a mantissa length of 23 bits. The result based on the Newton-Raphson iteration/s comprises a greater number of bits, and therefore the bits of the result that extend beyond the mantissa length specified by the IEEE 754 standard are removed (i.e. the result is truncated) and the LSB is rounded up or down in dependence upon the bits truncated from the mantissa.

An issue may arise during the rounding process, which is that, since the result based on the Newton-Raphson estimate is not known to infinite precision, the rounding process may result in a rounding in a different direction to the direction in which the true (infinite precision) result would be rounded. Reference is made to FIG. 4 , which shows a number line 400 illustrating floating point numbers increasing by one unit in the last place (ULP). In other words, the value of the mantissa increases along the number line 400 by the smallest graduation possible in single precision floating point format. The LSB of the mantissa has a value of 2⁻²³, and therefore, the number line 400 shows the floating point numbers: F−2⁻²³, F, F+2⁻²³. Although this example illustrates the case in which the floating point numbers are expressed in single precision, in some examples, the floating point numbers may be expressed at a different precision level, e.g. in half (16 bit) precision.

When the Newton Raphson method is applied to approximate a function, the output may not be exactly equal to a floating point number expressible in the single-precision. In the example, in FIG. 4 , the output of the Newton-Rapson approximation, lies between F and F+2²³. Since the output is closer to F, when the output is truncated and the LSB is rounded, the result will be equal to F. As can be seen in FIG. 4 , the true result (i.e. the infinite precision result) is within 1 ULP of the output of the Newton-Raphson approximation. Nevertheless, the true result lies within a different floating point interval such that it would round to a different floating point number. As shown in FIG. 4 , if the true result were truncated and rounded to a single precision floating point number, the rounded result would be F−2⁻²³. This is different to the rounded result of the Newton-Raphson approximation, which is F.

In order to correct for this rounding error, the execution unit is configured to perform a reversal operation of the function using the Newton-Rapson approximation to determine the error associated with the Newton-Raphson approximation. The magnitude and sign of the error is used to determine how to round the result from the Newton-Raphson approximation. The magnitude and sign of the error are used to select between one of three different values to which the result from the Newton Raphson approximation is rounded to.

In the example of FIG. 4 , if the result of the reversal operation indicates an error that is less than a predefined magnitude, then the approximation is rounded to the centre value (i.e. F): If |R(NR)|≤2⁻²⁴→Result=F  Eqn 6

If the result of the reversal operation indicates an error that is negative and greater than a predefined magnitude, then the approximation is rounded to the lower value (i.e. F−2⁻²³): If R(NR)<−2⁻²⁴→Result=F−2⁻²³  Eqn 7

If the result of the reversal operation indicates an error that is positive and greater than a predefined magnitude, then the approximation is rounded to the upper value (i.e. F+2⁻²³): If R(NR)>2⁻²⁴→Result=F+2⁻²³  Eqn 8

By applying this method, it may be ensured that the result from the Newton-Raphson approximation is rounded to the same floating point value that the true result would round to. Specific examples of the reversal operations will be given for the functions evaluated according to embodiments of the application.

As noted, embodiments of the application may be applied to evaluate several commonplace functions.

In some examples, the Newton Raphson method may be applied in combination with a look up table to evaluate a divide operation that is given by:

$\begin{matrix} {y = \frac{n}{d}} & {{Eqn}\mspace{14mu} 9} \end{matrix}$

To evaluate this divide operation, an estimate X, for the reciprocal of the divisor is first determined:

$\begin{matrix} {X \approx \frac{1}{d}} & {{Eqn}\mspace{14mu} 10} \end{matrix}$

In order to apply the Newton Raphson method to determine X, a function f(X) that is equal to zero at X=1/d is applied. Such a function is given by:

$\begin{matrix} {{f(X)} = {\frac{1}{X} - D}} & {{Eqn}\mspace{14mu} 11} \end{matrix}$

Using this function (ƒ(X)) in Eqn 4 above gives:

$\begin{matrix} {X_{n + 1} = {{X_{n} - \frac{{1\text{/}X_{n}} - d}{{- 1}\text{/}X_{n}^{2}}} = {X_{n}\left( {2 - {d\; X_{n}}} \right)}}} & {{Eqn}\mspace{14mu} 12} \end{matrix}$

Iteratively applying Eqn 12 enables an estimate for the reciprocal

$\left( \frac{1}{d} \right)$ of the divisor to be determined. A circuit comprising two multiplier circuits and an addition/subtraction circuit may be used to evaluate each iteration.

Eqn 12 is the first order Newton-Raphson for evaluating the reciprocal of a number. If the function (ƒ(X)) given in Eqn 11 is instead used in Eqn 5, then the second order Newton Raphson for evaluating a reciprocal may be derived: X _(n+1) =X _(n)(3−dX _(n)(3−dX _(n)))  Eqn 13

Hence, different orders of Newton Raphson may be applied to evaluate the reciprocal of the divisor. A multiplication may be applied between the evaluated reciprocal

$\left( \frac{1}{d} \right)$ and the dividend (n) to evaluate the divide operation:

$\begin{matrix} {y = {n*\frac{1}{d}}} & {{Eqn}\mspace{14mu} 14} \end{matrix}$

Once the approximation for the divide operation has been obtained from Eqn 14, the correction by reversal technique is applied. The reversal operation for the division is given by: R(y)=y*d−n  Eqn 15

The hardware module is configured to evaluate this function given by Eqn 15, and in dependence upon the value of R(y), determine how to round the LSB of the mantissa of the floating point number result. When the floating point number is a single precision number, the LSB of the mantissa is rounded as indicated by Eqns 6-8.

Reference is made to FIG. 5 a , which illustrates the first part of an example of the use of the pipeline 300 (or variations thereof) for evaluating a division operation of two numbers.

The numerator (n) and denominator (d) are received at the state element 505. The numerator and denominator may be delivered to the hardware module in response to the execution of a divide instruction. The numerator and denominator are operands of the divide instruction. The numerator and denominator are introduced to the pipeline during the first processing stage E₀, since a transport delay associated with delivering the values and control information associated with the operation to the hardware module prevents the values from being introduced prior to the first processing stage E₀. The numerator and denominator are both floating point numbers.

Each of the numerator and the denominator are delivered to respective unpack circuitry 510 a, 510 b. The unpack circuitry 510 a is configured to unpack the numerator into its respective sign (n_(s)), exponent (n_(e)), and mantissa (n_(m)) parts. The unpack circuitry 510 b is configured to unpack the denominator into its respective sign (d_(s)), exponent (d_(e)), and mantissa (d_(m)) parts.

The preparation circuit 515 is configured to check the exponent components (d_(e) and n_(e)) to determine if the exponents take one or more special values, and to output a relevant special result if so. The preparation circuit 515 is configured to determine if the difference between the numerator minus the denominator is greater than a predefined value such that the result would be too large to represent at the chosen precision level e.g. in single precision floating point format. In this case, a floating point number representing infinity is output as the result from the pipeline without requiring all of the usual steps in the pipeline to be carried out. Similarly, the preparation circuit 515 is configured to determine if the numerator minus the denominator is less than a predefined value such that the result would be too small to represent at the chosen precision level, e.g. in single precision floating point format. In that case, the floating point result that is output is zero.

Assuming that the floating point number does not take a special value, as discussed above, the prep circuitry 515 is configured to determine from the sign (d_(s), n_(s)) and exponent (n_(e), d_(e)) components, the sign (y_(s)) and exponent (y_(e)′) components for the result of the division operation. The exponent (y_(e)′) for the result can be calculated by performing a subtraction of the exponent (d_(e)) of the denominator from the exponent (n_(e)) of the numerator. Following this subtraction, the exponent (y_(e)′) may still need to be normalised in dependence upon the result of the calculation of the mantissa to yield the exponent result (y_(e)) which is packed into the final floating point result, as will be described later. The sign component (y_(s)) for the result can be calculated by comparing the sign (n_(s)) of the numerator with the sign (d_(s)) of the denominator. If n_(s) and d_(s) are the same (i.e. either both negative or both positive), then y_(s) will be positive. If n_(s) and d_(s) are different (i.e. one is negative and the other is positive), then y_(s) will be negative.

The preparation circuit 515 is also configured to normalise the components to specific ranges. The preparation circuit 515 is configured to ensure that the mantissa (d_(m)) of the denominator is within the correct bit-range of the internal state register. The preparation circuit 515 is also configured to adjust the exponent (d_(e)) to compensate for the adjustment to the mantissa (d_(m)).

The mantissa (d_(m)) of the denominator is used to search a look up table 520. The look up table 520 contains a series of estimates for the mantissa of the reciprocal of the denominator that can be used as starting values for the Newton-Raphson method. A subset of the bits of the mantissa of the denominator are used as an index into the look up table 520 to search the look up table to provide an initial estimate X₀ for the mantissa of the reciprocal. For example, the hardware module may use the 10 MSBs of the mantissa of the denominator as an index to search the look up table 520. After obtaining the initial estimate X₀ of the denominator from the look up table 520, the hardware module is configured to apply the Newton-Raphson method to determine a more precise estimate for the reciprocal.

The multiplier 320 c is configured to multiply the initial estimate (X₀) for the reciprocal with the denominator (d_(m)). In FIG. 6 , the output of this multiplication is labelled as Q, whereQ=d_(m)X₀.

The subtraction circuit 530 is configured to subtract Q from the number 3. This subtraction takes place during the sixth stage (E₅) of the pipeline. The variables (y_(s), y_(e)′, n_(m), d_(m), X₀, Q, 3-Q) received at the end of the pipeline are re-inserted at the start of the pipeline.

The multiplication circuit 320 a is configured to multiply 3−Q with Q. The multiplication circuit 320 b is configured to multiply n_(m) with X₀ to obtain an estimate for the mantissa of the result of the division based on the look up table output.

The subtraction circuit 536 is configured to subtract the output (Q(3−Q)) of the multiplier 320 a from the number 3.

The multiplier circuit 320 c is configured to multiply the output (3−Q(3−Q)) of the subtraction circuit 536 with the initial estimate (n_(m)X₀) of the mantissa of the divide result from the multiplier 320 b. The output of the multiplier 320 c provides an updated estimate (y_(m)″) for mantissa of the divide result. As can be seen from Eqns 13 and 14, multiplying the initial estimate (n_(m)X₀) with the factor 3−Q(3−Q) is equivalent to using Newton Raphson to determine an estimate for the reciprocal and then multiplying by the numerator.

The estimate (y_(m)″) of the mantissa for the divide result is passed to the circuit 540, which is configured to produce a normalised estimate (y_(m)′) of the mantissa.

Reference is made to FIG. 5 b , which illustrates the subsequent processing by the pipeline of the hardware module when evaluating the divide operation.

The multiplier 320 b is configured to multiply the estimate (y_(m)′) of the mantissa of the divide result by the denominator (d_(m)). This operation is part of the reversal operation used to determine the ULP of the mantissa of the divide result. The output (d_(m)y_(m)′) of the multiplier 320 b should be approximately equal to the mantissa (n_(m)) of numerator.

The ULP circuit 544 is configured to determine the Unit in the Last Place for the mantissa based on the output (d_(m)y_(m)′) from the multiplication of y_(m)′ and d_(m) carried out by the multiplier 320 b. The ULP circuit 544 comprises a subtraction circuit configured to subtract the numerator (n_(m)) from the output (d_(m)y_(m)′) of the multiplier as in Eqn 15. The ULP circuit 544 is then configured to compare the magnitude and sign of the resulting error value to the different limits (as given by Eqns 6 to 8) to determine a value for the ULP.

The ULP is passed to the Normalisation circuit 546, which is configured to normalise and truncate the estimated mantissa (y_(m)′) and set the determined ULP to the ULP for the truncated mantissa. The normalisation process may involve shifting the mantissa. The output of this process is the mantissa (y_(m)) in the length required by the floating point format of a particular precision level. The truncation process may truncate the mantissa length to the length (i.e. 23 bits) specified for single precision floating point format.

The normalisation circuit 546 is also configured to adjust the exponent (y_(e)′) to obtain the exponent (y_(e)′) of the result in dependence upon the amount of shifting performed to normalise the mantissa.

The pack circuitry is configured to pack the different components (y_(s), y_(e), y_(m)) into the floating point number result (y) of the divide operation. The result is output from the pipeline and provided to the worker thread that executed the divide instruction.

Therefore, the pipeline 300 can be used to implement the Newton-Raphson method in combination with a look up table to evaluate a division operation.

In some examples, the Newton-Raphson method can be applied to determine an estimate for the square root (z) of a floating point number (x). The square root function may be written as:

$\begin{matrix} {z = {\sqrt{x} = {\frac{x}{\sqrt{x}} = {r*x}}}} & {{Eqn}\mspace{14mu} 16} \end{matrix}$ where r is given by:

$\begin{matrix} {r = \frac{1}{\sqrt{x}}} & {{Eqn}\mspace{14mu} 17} \end{matrix}$

In order to apply the Newton Raphson method to determine r, a function f(r) that is equal to zero at r=1/√{square root over (x)} is applied. Such a function is given by: ƒ(r)=r ⁻² −x  Eqn 18

Using this function in the first order Newton-Raphson of Eqn 4 gives:

$\begin{matrix} {r_{n + 1} = {\frac{r_{n}}{2}\left( {3 - {xr_{n}^{2}}} \right)}} & {{Eqn}\mspace{14mu} 19} \end{matrix}$

Eqn 18 may, therefore, be used to iteratively determine the value of r. The initial value of r (i.e. r₀) is determined from a look up table of the hardware module. The value of r₀ is selected from the look up table in dependence upon the value of x. One or more Newton Raphson iterations are then applied to determine a value for r at a higher level of precision.

Once r is determined at the higher level of precision, Eqn 16 is applied to determine the value of the square root (z).

Once the approximation for the square root has been obtained using the Newton-Raphson method, the correction by reversal technique is applied. The reversal operation for the division is given by: R(z)=z ² −x  Eqn 20

The hardware module is configured to evaluate this function given by Eqn 20 and, in dependence upon the value of R(y), determine how to round the LSB of the truncated mantissa of the floating point number result. When the floating point number is a single precision floating point number, the LSB of the truncated mantissa is rounded as indicated by Eqns 6-8.

Reference is made to FIG. 6 a , which illustrates an example of processing by the pipeline 300 used to evaluate the square root of a floating point number. According to embodiments of the application, variants of the pipeline 300 may also be used to evaluate the square root.

The execution unit is configured to execute an instruction comprising an op code and an operand. The op code indicates a square root function that is to be evaluated by the execution unit. The operand is the input floating point number (x) of which the square root is to be determined. The input floating number (x) is provided to the pipeline of the execution unit. A state element 602 of the pipeline receives the input floating point number (x), the square root of which is to be determined. The input floating point number (x) is passed to the unpack circuitry 604, which is configured to extract the sign bit (x_(s)), exponent (x_(e)) and mantissa (x_(m)) from the input (x).

The preparation circuit 606 receives the extracted exponent (x_(e)) and mantissa (x_(m)) and performs any necessary preparation on these values. The preparation circuit 606 is configured to check the components to determine if the components take one or more special values, and output a relevant special result if so. For example, if the sign bit (x_(s)) is negative then the result of the square root function will be a NaN, irrespective of the values of the mantissa and exponent. Therefore, a NaN may be output as the result from the pipeline without requiring all of the usual steps in the pipeline to be carried out. Similarly, the preparation circuit 606 is configured to determine if x has a value less than a predefined value, such the result is too small to represent at the chosen precision level e.g. in single precision floating point format. In this case, the result output is zero. Similarly, the preparation circuit 606 is configured to determine if x has a value larger than a predefined value, such that the result is too large to represent at the chosen precision level, e.g. in single precision floating point format. In that case, the result output is infinity.

The preparation circuit 606 is also configured to normalise the components to specific ranges. The exponent (x_(e)) is made even (if it is not already) by subtracting 1 from the exponent. This allows the exponent to be divided by 2 by as described later. To compensate for the subtraction of 1 from the exponent, the mantissa (x_(m)) is shifted to the left by one bit. The sign bit (x_(s)) is the sign bit (z_(s)) for the final result, and is stored to be packed with the other components later.

The mantissa (x_(m)) is then used to search the look up table 608 so as to output from the look up table an estimate (r₀) of the reciprocal of the square root of x_(m).

The look up table 608 comprises a plurality of entries, each providing an estimate for the reciprocal of the square root of a value. The mantissa (x_(m)) of the input is used to search the look up table for such an estimate (r₀) for an estimate of the mantissa of the reciprocal of the square root of x, which is output from the table and then used as an initial value for applying the Newton-Raphson method to determine a more precise estimate for the mantissa of the reciprocal of the square root. The look up table 608 is searched using a subset of bits of the mantissa (x_(m)) as an index value. For example, the look up table 608 may be searched using the 10 most significant bits of the mantissa (x_(m)).

The output (r₀) from the look up table 608 is provided to the multiplier 320 c, which is configured to multiply r₀ by itself. In other words, the multiplier 320 c is configured to determine the square of r₀.

The multiplier 320 a receives r₀ ² and multiplies this with x_(m) to obtain x_(m) r₀ ². The subtraction circuit 614 is then configured to subtract x_(m) r₀ ² from the number 3.

The multiplier 320 c is configured to multiply the output (3−x_(m)r₀ ²) of the subtraction circuit 614 with half the value from the look up table (r₀/2) to obtain the updated estimate (r₁) for the mantissa of the reciprocal of the square root of x. This is the result of one iteration of the first order Newton-Raphson method, which doubles the number of known bits of the reciprocal of the square root of x. Another iteration will then be performed so as to again double the number of known bits.

Reference is now made to FIG. 6 b , which illustrates the continuation of the process (which has so far been described with reference to FIG. 6 a ) for determining the square root of a floating point number (x).

The updated estimate (r₁) for the mantissa of the reciprocal of the square root following the first iteration is provided to the multiplier 320 a, which is configured to determine the square of r₁.

The multiplier 320 c is configured to multiply x_(m) with the square (r₁ ²) determined by the multiplier 320 a. The result (x_(m)r₁ ²) from the multiplier 320 c is provided to the subtraction circuit 622, which is configured to subtract x_(m)r₁ ² from the number 3.

During the next traversal of the pipeline, the multiplier 320 a is configured to multiply 3-x_(m)r₁ ² with r₁/2 to generate the estimate (r₂) of the mantissa for the reciprocal of the square root following two iterations of the first order Newton Raphson.

Unlike in the example given for the divide operation, two iterations of Newton Raphson are used during the calculation of the square root. In the divide example, only a single iteration is required to generate an estimate of the required precision for a single precision floating point result since a second order Newton-Raphson (which triples the number of known bits each iteration) is used. On the other hand, in the square root example, two iterations are used to generate an estimate of the required precision for a single precision floating point result since a first order Newton-Raphson (which doubles rather than triples the number of known bits each iteration) is used.

Following the generation of the estimate (r₂) for the mantissa of the reciprocal of the square root, the multiplier 320 c is configured to multiply r₂ with x_(m) to obtain a mantissa value (z_(m)) for the square root of x.

Reference is now made to FIG. 6 c , which illustrates the continuation of the process (which has so far been described with reference to FIGS. 6 a and 6 b ) for determining the square root of a floating point number (x).

The process for performing the correction by reversal is shown in FIG. 6 c . The square root value (z_(m)) is supplied to the multiplier 320 a, which is configured to determine the square (z_(m) ²) of z_(m). The square (z_(m) ²) will be approximately equal to the input value x_(m), for which the square root was calculated. The value z_(m) ² is passed to the ULP circuit 630.

The ULP circuit 630 is configured to determine the Unit in the Last Place (ULP) for the truncated mantissa in dependence upon the output (z_(m)) of the multiplier 320 a. The ULP circuit 630 comprises subtraction circuitry configured to subtract the input variable (x_(m)) from the square (z_(m) ²) of the result (z_(m)) as in Eqn 20. The ULP circuit 630 is then configured to compare the magnitude and sign of the resulting error value to different limits (as given by Eqns 6 to 8) to determine a value for the ULP.

The ULP circuit 630 in this example is also configured to normalise and truncate the estimated mantissa (z_(m)) and add the determined ULP to the truncated mantissa. Alternatively, one or more of these steps may be performed by additional circuitry that is separate from the ULP circuit 630. The normalisation process may involve shifting the mantissa. The output of this process is the mantissa (z_(m)′) in the length required by the floating point format of a particular precision level. The truncation process may truncate the mantissa length to the length (i.e. 23 bits) as specified for single precision floating point format.

The ULP circuit 630 is also configured to adjust the estimate of the exponent (x_(e)) to obtain the exponent (z_(e)) of the result. The amount of adjustment to the exponent is dependent upon the amount of shifting required to normalise the mantissa. The exponent is also divided by two as a result of the square root operation. This modification to the exponent could be carried out by another component of the pipeline and may be carried out by the preparation circuit 606.

The final normalised components (z_(s), z_(e), z_(m)′) for the floating point result are then passed to the pack circuit 632, which is configured to pack the components to provide the floating point result (z) for the square root of x. The sign component (z_(s)) is set equal to the sign (x_(s)) of the input variable, assuming that the input variable (x) has a positive value.

Therefore, the hardware module enables a square root operation to be evaluated using multiplication and addition/subtraction operations.

The multiplier circuit of the hardware module may also be used for the evaluation of logarithms. The hardware module is configured to apply different methods to evaluate a logarithm for different parts of the input range.

If a logarithm to be evaluated is given by ln(x), and x<e^(1/16), the following Taylor series is taken to apply:

$\begin{matrix} {{\ln(x)} = {{\ln\left( {1 + \delta} \right)} \approx {\delta - \frac{\delta^{2}}{2} + {\frac{\delta^{3}}{3}\mspace{14mu}\ldots}}}} & {{Eqn}\mspace{14mu} 21} \end{matrix}$

The multiplier circuit can be used to evaluate this Taylor expansion within the indicated input range in order to evaluate ln(x). This approximation for ln(x) may be implemented in the processing pipeline 300 by using an addition/subtraction circuit in the preparation block 410 to determine δ, and then by supplying δ as an input to the multiplier circuits 320 a, 320 b, and 320 c as applicable to determine each item of the polynomial series in Eqn 21. Each item of the polynomial series may then be summed or subtracted from the preceding item using an addition circuit in the processing pipeline. The addition circuits are described in more detail in relation to determining the logarithmic function when x≥e^(1/16) as laid out in the following. The same addition/subtraction circuits in the same processing pipeline may be used to determine the logarithmic function for both ranges of x.

The mathematical derivation for the method applied when x≥e^(1/16) is given below, followed by its application in the processing pipeline 300. If x≥e^(1/16), then ln(x) is evaluated using the expression:

$\begin{matrix} {{\ln(x)} = {{\ln\left( c_{k} \right)} + {\ln\left( \frac{x}{c_{k}} \right)}}} & {{Eqn}\mspace{14mu} 22} \end{matrix}$ where c_(k) is given by:

$\begin{matrix} {c_{k} = {1 + \frac{k}{64}}} & {{Eqn}\mspace{14mu} 23} \end{matrix}$ k is an integer chosen from the set k∈{0, 1, . . . , 64}, such that

${{x - c_{k}}} \leq {\frac{1}{128}.}$ In this case x/c_(k) is close to 1.

A look up table is provided in the hardware module for looking up the value of ln(c_(k)). The look up table comprises 64 entries, with there being a separate entry for each of the values of k.

Since

${{{x - c_{k}}} \leq \frac{1}{128}},$ then x/c_(k) is close to one such that a Taylor series approximating ln

$\left( \frac{x}{c_{k}} \right)$ may be made use of. The Taylor series that approximates In

$\left( \frac{x}{c_{k}} \right)$ is evaluated using the processing pipeline according to embodiments of the application.

When evaluating ln

$\left( \frac{x}{c_{k}} \right),\frac{x}{c_{k}}$ may be re-written as:

$\begin{matrix} {\frac{x}{c_{k}} = \frac{1 + \frac{r}{2}}{1 - \frac{r}{2}}} & {{Eqn}\mspace{14mu} 24} \end{matrix}$ where:

$\begin{matrix} {r = \frac{2\left( {x - c_{k}} \right)}{\left( {x + c_{k}} \right)}} & {{Eqn}\mspace{14mu} 25} \end{matrix}$ ln

$\left( \frac{x}{c_{k}} \right)$ may then be approximated as:

$\begin{matrix} {{\ln\left( \frac{x}{c_{k}} \right)} \approx {2\left( {\frac{r}{2} + {\frac{1}{3}\left( \frac{r}{2} \right)^{3}\mspace{14mu}\ldots}}\mspace{14mu} \right)}} & {{Eqn}\mspace{14mu} 26} \end{matrix}$

The processing pipeline according to examples of the application is applied to evaluate the Taylor series given by Eqn 26. The substitution given by Eqn 24, therefore, allows the even powers to be eliminated from the Taylor series expansion of ln(x/c_(k)).

In order to determine the value of r, the Newton-Raphson method and look up table for the divide function, as discussed above, is applied. Taking the denominator to be (x+c_(k)), the reciprocal (R) of the denominator may be evaluated by determining an initial value (R₀) from a look up table and then applying Eqn 13 to determine a more precise estimate (R₁): R ₁ =R ₀(3−(x+c _(k))R ₀(3−(x+c _(k))R ₀)  Eqn 27

The value for r in Eqns 24 to 26 is then given by: r=2(x−c _(k))*R ₁  Eqn 28

The result of the Taylor series expansion is then added to the value for ln(c_(k)) that is derived from the look up table to determine the value of ln(x):

$\begin{matrix} {{\ln(x)} = {{\ln\left( c_{k} \right)} + r + \frac{r^{3}}{12}}} & {{Eqn}\mspace{14mu} 29} \end{matrix}$

The terms higher than r³ are small enough that, for most purposes, they can be ignored.

Once ln(x) has been evaluated, a multiplication is optionally applied to determine the log in a different base. For example, to determine the log to the base ‘a’ of x, the following is applied: log_(a)(x)=ln(x)*log_(a)(e)  Eqn 30

Eqn 30 may, for example, be applied to determine log₂(x).

Reference is made to FIG. 7 a , which illustrates the use of the pipeline 300 (or variations thereof) in the hardware module for evaluating the logarithm of an input value.

The execution unit is configured to execute an instruction comprising an op code and an operand. The op code indicates a logarithm that is to be evaluated by the execution unit. The operand is the input floating point number (x) of which the logarithm is to be determined. The input floating number (x) is provided to the pipeline of the execution unit.

The input value (x) is received at the state element 702. The input value (x) is passed to the unpack circuit 704, which is configured to unpack the separate components, i.e. the sign bit (x_(s)), the exponent (x_(e)), and the mantissa (x_(m)) from the input value (x).

The components are received at the preparation circuit 706, which is configured to check the components to determine if the components take one or more special values. For example, if the sign bit (x_(s)) is negative then an error is flagged, irrespective of the values of the mantissa and exponent.

The preparation circuit 706 may also modify the sign component (x) in dependence upon the exponent and mantissa components. If x<1, then the logarithm result will be negative. Therefore, in this case the sign component (x_(s)′) for the result is set to be negative. This sign component (x_(s)′) will be packed with the calculated exponent and the calculated mantissa for the result, once, the pipeline has determined the mantissa of the result. If x>1, then the logarithm result will be positive, and the sign component (x_(s)′) remains unchanged from the input sign component (x_(s)).

The preparation circuit 706 is configured to determine based on the input range in which the input value falls, which method is to be applied to evaluate the logarithm. If x<e^(1/16), then the hardware module is configured to evaluate the logarithm by evaluating the Taylor expansion given in Eqn 21. Otherwise, the hardware module is configured to evaluate the logarithm by evaluating the expression given by Eqn 22.

In the example illustrated in FIGS. 7 a, 7 b, and 7 c , x≥e^(1/16) and therefore, the preparation circuit 706 determines that the method making use of the Taylor expansion in Eqn 21 is to be applied. The control circuitry 330 of the pipeline 300 configures the elements of the pipeline to apply this method to the input variables.

The preparation circuit 706 is configured determine based on the value of x, a value for k—and hence a value for c_(k) given by Eqn 23 such that |x−c_(k)|≤1/128. When the value for k is determined, the corresponding value for ln(c_(k)) is loaded from a look up table of the preparation circuit 706. The preparation circuit is configured to use an index value (which may be either k or c_(k)) to locate the corresponding value of ln(c_(k)) from the look up table.

The mantissa (x_(m)) of the input value and the value of c_(k) are provided to an addition circuit 708 that is configured to calculate the value of x_(m)+c_(k). The mantissa (x_(m)) of the input value and the value of c_(k) are also provided to the subtraction circuit 710 that is configured to calculate the value of (x_(m)−c_(k)).

During the next traversal of the pipeline, the look up table 712 is configured to provide an estimate of the reciprocal of x_(m)+c_(k). The value of x_(m)+c_(k) is used to search the look up table 712 for an estimate for the reciprocal. A subset of bits of the value of x_(m)+c_(k) are used as index to search the look up table from which the corresponding reciprocal estimate (R₀) is output.

The multiplier 320 c is configured to multiply together R₀ with (x_(m)− c_(k)) and the constant 2 to determine 2R₀(x_(m)−c_(k)).

Reference is now made to FIG. 7 b , which illustrates the continuation of the process (which has so far been described with reference to FIG. 7 a ) for determining the logarithm of a floating point number.

The estimate (R₀) for the reciprocal value taken from the look up table is multiplied using multiplier 320 a against x_(m)+c_(k) to produce R₀(x_(m)+c_(k)), which is labelled in FIGS. 7 b and 7 c as ‘q’.

The subtraction circuit 718 is configured to subtract q from the number 3 to produce 3−q, which is provided to multiplier 320 c. Multiplier 320 c is configured to receive 3−q and q and multiply them to determine q(3−q).

The subtraction circuit 722 is configured to subtract q(3−q) from the number 3 to determine 3−q(3−q).

The multiplier circuit 320 a is configured to multiply 3−q(3−q) with 2R₀(x_(m)−c_(k)) to calculate r_(m)′. r_(m)′ is the mantissa of the value for r in Eqns 24 to 26, prior to the normalisation and shift process.

It is seen that, together, the multipliers 320 c, 320 a, along with the subtraction circuits 718, 722 are configured to perform a second order Newton-Raphson iteration as indicated by Eqn 27, which enables r_(m)′ to be determined using Eqn 28.

Once the value r_(m)′ is determined, this is passed to the normalisation and shift circuit 726. This circuit 726 performs a shift of the mantissa r_(m)′ so as to correct for uncertainty regarding the position of the leading bit. This circuit 726 shifts the mantissa by, at most, 3 bits. The normalised mantissa is indicated by r_(m).

The mantissa (r_(m)) of r is then passed to the multiplier 320 c, which is configured to determine the square (r_(m) ²) of r_(m).

Reference is now made to FIG. 7 c , which illustrates the continuation of the process (which has so far been described with reference to FIGS. 7 a and 7 b ) for determining the logarithm of a floating point number.

The multiplier 730 is configured to multiply the square (r_(m) ²) by r_(m), to determine the cube (r_(m) ³) of the mantissa of r.

The multiplier 320 c is configured to multiply the cube (r_(m) ³) of the mantissa of r by one twelfth to obtain

$\frac{r_{m^{\prime}}^{3}}{12} \cdot \frac{r_{m^{\prime}}^{3}}{12}$ is the mantissa of the value for

$\frac{r^{3}}{12}$ in Eqn 26, prior to the normalisation and shift process.

It is seen that, together, the multipliers 320 a and 320 c, are configured to determine from the value of r provided to them, the value of

$\frac{r^{3}}{12}$ for use in the Taylor expansion given in Eqn 29.

The value of

$\frac{r_{m^{\prime}}^{3}}{12}$ is passed to the normalisation and shift circuit 734 that is configured to normalise and shift this mantissa value so as to align the exponent of

$\frac{r^{3}}{12}$ with the exponent of r. The operation of cubing r will likely result in change to the exponent. However, the exponent is not modified by the multipliers, but only the mantissa is modified. To account for the change that would occur to the exponent, the mantissa

$\frac{r_{m^{\prime}}^{3}}{12}$ is shifted to be aligned with r. This shifting allows the addition of

$\frac{r_{m^{\prime}}^{3}}{12}$ and r carried out between the adder 736.

The at least one adder 736 is configured to add

$\frac{r_{m^{\prime}}^{3}}{12},$ r_(m), and ln(c_(k)) together as in Eqn 29. The at least one adder 736 may be implemented as an adders taking three inputs and producing the result or as a set of two of adders, used to perform the overall addition. The result is the natural logarithm (ln(x_(m))) of the mantissa of x, which is provided to the normalisation circuit 738, which is configured to adjust this result from the adder 736 to produce the mantissa (ln(x)_(m)) of the natural logarithm of x. The normalisation circuit 738 uses the exponent (x_(e)) to calculate x_(e)*ln(2) using a constant multiplier. The value of x_(e)*ln(2) is added to the value derived from the addition circuit 736 to generate ln(x)_(m).

The normalisation circuit 738 is also configured to calculate the exponent (x_(e)′) of the result in dependence upon the normalisation applied to the mantissa (ln(x)_(m)) of the result.

ln(x)_(m) is received at the constant multiplier 740, which is configured to optionally convert the logarithm into a different base. The multiplier 740 receives ln(x)_(m) and multiplies it by log_(a)(e) to produce log_(a)(x)_(m). log_(a)(x)_(m) may be log₂(x)_(m). The length of the mantissa (ln(x)_(m)), which is provided in FP32 format (23 bits) is extended by multiplying the mantissa by a 33 bit value for log_(a)(e) to produce a 33 bit value for log_(a)(x)_(m). The normal mantissa length is 23 bits in FP32 format, but increasing the length of the mantissa to 33 bits gives better accuracy. The inventors have determined empirically that a mantissa length of 33 bits is a good trade-off between complexity and accuracy when calculating a logarithm function.

log_(a)(x)_(m) is passed to the pack circuit 742, which is configured to pack the components (x_(e), x_(s), log_(a)(x)_(m)) into a floating point result, log_(a)(x). This result is output from the pipeline and provided to the worker thread that executed the instruction to generate the logarithm.

The processing pipeline 300 may be applied for evaluating exponential functions. Examples will now be described of the use of such a pipeline 300, or similar variations of such a pipeline, for evaluating exponential functions. The aim is to provide a result in floating point format of e^(x), where x is an input value. The first step in using the multiplier configuration of FIG. 3 to evaluate the exponential function is to recognise certain properties of the floating point format, and its relationship to certain mathematical properties of exponential functions. Looking at FIG. 8 , this represents a set of bits representing a number in the FP32 format, but with an expanded mantissa. The normal mantissa length is 23 bits in FP32 format, but increasing the length of the mantissa to 33 bits gives better accuracy. The inventors have determined empirically that a mantissa length of 33 bits is a good trade off between complexity and accuracy when calculating an exponential function. Bit S is the single sign bit. The E bits represent the exponential bits which denote an integer value. The M bits denote bits of the expanded mantissa. As explained already, there is a single sign bit and 8 exponential bits. The length of the mantissa is extended by multiplying the FP32 format mantissa (23 bits) by a 33 bit value for log₂(e).

In floating point format, the exponent bits are used as described in the background section. That is, when the number 2 is raised to the power of the exponent bits (minus the offset), and multiplied by the mantissa value then the number which is represented by the floating point format representation is given. By reorganising the exponential function such that it can be re-written as the product of two powers of two, it is possible to treat an integer part and a fractional part separately. This can be derived as shown: e ^(x) =e ^(x. ln(2). log 2(e))  Eqn 31 e ^(x) =e ^((i+f)ln(2))  Eqn 32 where (i+f)=x.log 2(e). i is an integer and f is a fractional part e ^(x) =e ^(i. ln(2)) ·e ^(ƒ. ln(2))  Eqn 33 e ^(x)=2^(i)·2^(ƒ)  Eqn 34

Similarly, for base-2 exponentials (2^(x)), the following formula can be used to convert them: 2^(x)=e^(x ln 2) such that they can similarly be approximated by the following techniques. Reverting to Eqn 31, the constant log_(2(e)) is used to pre-multiply the exponential with natural log, ln(2), so that the result can be split into two separate numbers, one which can represent the integer part and one which can represent the fractional part. The integer part i then forms the exponent of the result, and the fractional part may be split as will now be described. Returning to the FP format representation, the final value is given by 2^([exp])×M. Therefore, i represents the exponent in the floating point value. Thus, the exponent bits in the floating point representation of the exponential result are the binary representation of i. Therefore, it is not necessary to evaluate 2^(i) any further. The mantissa bits represent 2^(ƒ), which must be evaluated.

To evaluate 2^(f), the f can be split into sub-components: ƒ=ƒ₀+ƒ₁+ƒ₂+ƒ₃ Therefore, 2^(f) may be written as: 2^(ƒ)=2^(ƒ) ⁰ ·2^(ƒ) ¹ ·2^(ƒ) ² ·2^(ƒ) ³

Each of the separate components f₀ . . . f₃ represents a bit slice of f. For example, for the following example value of f (by way of example only where f is 8 bits long), the respective components are indicated:

-   -   ƒ=11111111     -   ƒ₀=11000000     -   ƒ₁=00110000     -   ƒ₂=00001100     -   ƒ₃=00000011

A look up table or estimation is used to evaluate the separate components of 2^(f). In the above example, bit slices are each of the same length. However, the inventors have recognised that it can be particularly efficient to cause the bit slices to be are of varying length, such that they can be handled by look up tables or estimation, depending on their significance.

What is needed is to generate an accurate value for 2^(f) for each component f.

An exponential can be represented as a Taylor Series as follows:

$\begin{matrix} {e^{x} = {\frac{1 + x}{1!} + \frac{x^{2}}{2!} + \frac{x^{3}}{3!} + \ldots}} & {{Eqn}\mspace{14mu} 35} \end{matrix}$

Therefore, 2^(ƒ) can be estimated as:

$\begin{matrix} {2^{f} = {1 + \frac{f\mspace{11mu}\ln\mspace{11mu} 2}{1!} + \frac{\left( {f\mspace{11mu}\ln\mspace{11mu} 2} \right)^{2}}{2!} + \ldots}} & {{Eqn}\mspace{14mu} 36} \end{matrix}$

The series are infinite, but it will readily be appreciated that, for small values of x or f, the later components rapidly become vanishingly small.

The aim is to select a length of each bit slice such that look up tables can be efficiently stored and accessed, and conversely that if a slice is estimated, it can be done without loss of accuracy.

One aim therefore is to keep the highest order bit slice to be short, such that the look up table may contain a smaller number of entries, although each entry may be longer. Note that the length of an entry is governed amongst other things by the number of bits of precision that is used. In this example, 33 bits precision is utilised, and each entry in the look up table for the most significant bit slice constitutes 33 bits. If the length of the most significant bit slice is 4, as in the present example, the number of entries in the look up table is 2⁴ (16), and each entry has a length of 33 bits.

Note that for the next order bit slice, there is no need to store values for the bits preceding it in the mantissa. That is, the bits which correspond to the most significant bit slice would all be zeroes when considering the next order bit slice. Thus, the length of entries in the look up table for the next order bit slice is 33−4=29. If the second order bit slice is 5 bits long as in the present example, the number of entries is 2⁵, that is 32. Similarly, for the following next order bit slice, there is no need to store the leading zeroes and so the number of bits in each entry is 33−9 (24). If the number of bits in the bit slice is 7, the number of entries in the look up table is 2⁷(128). Thus, by varying the length of the bit slices in this way, the look up tables can be sized to select the number of entries and the length of the entries in the most appropriate way.

Note that the above numbers are exemplary only, other arrangements are possible, and it is also possible that two or more of the leading order bit slices have the same length.

When considering the least significant bits slice, based on 33 bit precision, the 17 bits of this bit slice represent a value which when expanded by the Taylor series would be such that any terms beyond the first order would exceed the precision length. It is therefore possible to calculate this term in the first order (1+fln2) rather than utilising a look up table and still achieve the necessary accuracy parameters. The length of the least significant bit slice may be half the total length of the expanded mantissa (e.g. 16 or 17 bits long)—its length is governed by the extent to which its estimate 1+fln2 is accurate within the given precision.

FIG. 9A shows four bit slices of the expanded mantissa M_(x)[FP32] in one example, labelled as follows:

a—bits 32 to 29

b—bits 24 to 28

c—bits 17 to 23

d—bits 0 to 16

Three of these may be used to access a respective look up table as shown in FIG. 9A. Look up tables are labelled LUTa, LUTb and LUTc as associated with their input bit slices a, b, c respectively. In one example, look up table LUTa has 16 entries, LUTb has 32 entries and LUTc has 128 entries each. As explained above, each entry is a value which is 2-, where y represents the value of the bit slice fed to that look up table.

The least significant component (f_(c)) is calculated as. 2^(ƒ) ^(c) =1+f _(c)·ln(2)  Eqn 37

The look up tables may be used to evaluate all but the smallest of the components (i.e. f₃ in the above example). f₃ may then be determined using Equation 37 as shown above.

The separate components are then multiplied together using the processing pipeline according to embodiments of the application to obtain a value for 2^(f). Therefore, a mantissa value 2^(f) is obtained for the exponential result (e^(x)) of input value x in addition to the exponent.

Reference is made to FIG. 10 , which illustrates the use of a processing pipeline according to embodiments of the application for evaluating an exponential function. This example may be used for evaluating an exponential function of a single-precision floating point number.

The input number is extracted from a computer instruction which has an opcode defining the exponential function and an operand which is, or points to, the input number. The hardware module is configured to provide the number to the processing pipeline just prior to the second stage E₁ of processing. Therefore, the number skips a first stage of processing during an initialisation run through the pipeline. During the initialisation run through of the pipeline, the number is delivered first to unpack circuitry 1005, which is configured to unpack the exponent Ex, mantissa Mx, and sign bit Sx from the input floating point number x. The unpacked parts of the number are then delivered to a pre-multiplier and preparation circuitry 1010. The pre-multiplier and preparation circuitry 1010 determines from the number an integer part and a fractional part. That is, the pre-multiplier and preparation circuit determines x.log₂ e to generate i+f, and then determines i as the largest integer leaving only f, the fractional component. The binary representation of i forms the exponent Ey of the result value, which is stored in a register until the final pass of the pipeline. The fractional part must be evaluated, as discussed above, in order to determine the mantissa of the result. The pre-mul and prep circuitry 1010 may also evaluate the least significant component 2^(f3) of the fractional part using Equation 37 as shown above, from bits 0 to 16 of the expanded mantissa.

In order to evaluate the fractional part, the bit slices a, b, c are passed to at least one look up tables LUTa, b, c in block 1015. The hardware module is configured to access from the look up tables 1015, the entry for each of the plurality of components 2^(ƒ) ⁰ , 2^(ƒ) ¹ , 2^(ƒ) ² of the fractional part.

The different evaluated components (i.e. 2^(ƒ) ^(c) ) are held in a register, ready to be further processed by the pipeline.

The different evaluated components of the fractional part are then processed together using the processing pipeline of multipliers. In this example, the multipliers are applied in series only and multiplication takes place over two runs through the pipeline. However, in other examples, two or more of the multipliers may be arranged in parallel (as illustrated in the example of FIG. 3 ) so as to perform the multiplications of different components of the fractional part in parallel.

As shown, at the pipeline pass #1 of the pipeline, two of the evaluated components 2^(ƒ) ⁰ , 2^(ƒ) ¹ are provided to the multiplier 320 a, which is configured to multiply these two components together and to output the result of the multiplication. The pipeline multiplexers are controlled to cause the result of the multiplication at multiplier 320 a to bypass multiplier 320 c and be delivered onwards to the end of the pipeline.

The other two evaluated components 2^(f2), 2^(f3) are switched to bypass multiplier 320 a and to arrive at latch 1025. These components are input to multiplier 320 c, which multiplies these two components together and outputs the results of the multiplication. The results from the two multiplications during the pipeline pass #1 are then stored in a register ready for a final run through the pipeline.

The results from the multiplications performed by multipliers 320 a and 320 c are passed to multiplier 320 b, which is configured to multiply together these two results to obtain a mantissa My for the output value for the exponential function. The mantissa is then provided to a packing circuit 1045. The packing circuit 1045 is configured to take the mantissa My resulting from the multiplication at multiplier 320 b and pack it with the exponent Ey determined by the pre-multiplier and prep circuit 1010 to determine a floating point representation for the exponential result (e^(x)).

Although the present example describes splitting the fractional part into four components (four bit slices of the input mantissa), it will be appreciated that other numbers of components may be used. A larger number of components requires a greater number of multiplications to be carried out, but reduces the necessary size of the look up table/s. A smaller number of components requires larger look up tables, but reduces the number of multiplications that must be carried. There exists a trade off between these considerations. Moreover, at least some of the bit slices may have differing lengths, which enables a further optimisation of the trade-off between the size of the look up tables and the number of multiplications, without compromising on accuracy.

Reference is made to FIG. 11 , which illustrates the use of a processing pipeline according to embodiments of the application for evaluating an exponential function of a half-precision floating point number.

The input x is extracted by the hardware module (from the instruction itself or from memory or a register). The hardware module is configured to provide the number to the processing pipeline just prior to the second stage E₁ of processing. Therefore, the number skips a first stage of processing during the initialisation run through the pipeline. During the initialisation run through of the pipeline, the number is delivered first to the unpack circuitry 1005, which is configured to unpack the exponent Ex, mantissa Mx, and sign bit Sx from the input floating point number. The number is then delivered to pre-multiplier and preparation circuitry 1010. The pre-multiplier and the preparation circuitry 1010 determines from the number, an integer part (corresponding to the exponent of the result Ey, as discussed above) and a fractional part. The fractional part must be evaluated, as discussed above, in order to determine the mantissa of the result. The pre-multiplier and prep circuitry 1010 may evaluate one or more components of the fractional part using Equation 37 as shown above.

In order to evaluate the fractional part, the fractional component a′ is passed to a look up table in block 1015. The hardware module is configured to access from the look up table 1015, the entry for component a′ of the fractional part. In the case of a half-precision floating point number, the fractional part may be divided into only two components, corresponding to two bit slices a′, b′ of the mantissa Mx. The look up table LUT a′ may be used to evaluate only one of these components 2^(ƒ) ⁰ ′, with the remaining component 2^(ƒ) ¹ ′ being evaluated using Equation 37 given above. FIG. 9B shows operation to generate the fractional components in half precision floating point. Note that the mantissa has been extended to a greater number of bits than normal FP16 precision (in this case 23 bits). This can be achieved by using a value for log₂(e) of a suitable length (e.g. 23 bits), as in the case of the FP32 example.

The evaluated components (i.e. 2^(ƒ) ^(c) ) are shared in a register, ready to be further processed by the pipeline.

In this example, there are only two evaluated components and so only a single multiplier 320 a is used to multiply these components together to produce the mantissa My of the function result. The mantissa is then provided to the packing circuit 1045. The packing circuit 1045 is configured to take the mantissa resulting from the multiplication at multiplier 320 a and pack it with the exponent Ey determined by the pre-mul and prep circuit 1010 to determine a floating point result for the mantissa.

Therefore, the hardware module described comprising the processing pipeline 300 (or variations thereof) is configured in response to the execution of suitable instructions by an execution unit to evaluate exponential, logarithm, division, and square root function as described. The hardware module is part of the execution unit and is configured to perform the calculations of the function in response to the execution of an appropriate instruction by a thread of the execution unit.

Reference is made to FIG. 12 , which illustrates an example of the use of such a hardware module 24 for performing the evaluation of functions in an execution pipeline of a processor. FIG. 12 shows a schematic block diagram of an execution unit 2 arranged to execute an instruction to evaluate a function, such as an exponential, logarithm, divide or square root. The instruction is executed by a worker thread, as described above with reference to FIG. 2 .

The execution unit 2 forms part of a pipeline 4 in a processing unit. The processing unit comprises an instruction fetch unit 6 which fetches instruction from an instruction memory 10. The processing unit also comprises a memory access stage 8 which is responsible for accessing a data memory 12 for loading data from the memory or storing data into the memory. A set of registers 14 is provided for holding source and destination operands for the instructions being executed at any instance by the execution pipeline 4. It will readily be understood that the execution pipeline 4 may contain many different types of execution unit for executing a variety of different instructions, for example for performing mathematical operations. The processing unit may be configured to execute a plurality of concurrent worker threads that are each allocated time periods by a supervisor thread.

The execution unit 2 comprises an instruction execution module 23 and an output buffer 27 for holding the result of execution of the instruction. The instruction execution module 23 is configured to execute an instruction to cause the hardware module 24 to evaluate a function of one or more input values. The instruction contains an op code that specifies the function to be evaluated by the hardware module 24. The instruction also contains at least one operand with respect to which the function is to be performed. When the instruction is executed, the execution unit supplies to the hardware module 24, the at least one operand and control information dependent upon the op code that causes the hardware module 24 to evaluate the function for the at least one operand. The hardware module receives the control information, which is used to control the multiplexors of the processing pipeline so as to implement the function specified by the op code using the multipliers and additional processing circuitry of the pipeline.

The one or more input values for the function are provided as an operand of the executed instruction. The hardware module 24 is configured in response to such an instruction to read one or more input values from the input buffer 25. The hardware module 24 then provides the result/s of the function in the output buffer 27.

It will be appreciated that the embodiments described are by way of non-limiting examples only, and that variations within the scope of the claims may be envisaged. In one variation, while the examples have been given in the context of floating point numbers of single precision and half precision formats, the technique may readily be adapted to floating point formats of different precisions. 

The invention claimed is:
 1. An execution unit for a processor, the execution unit comprising a hardware module having a processing pipeline configured to perform calculations to evaluate a first mathematical function, wherein the processing pipeline comprises a plurality of stages through which the calculations for evaluating the first mathematical function progress to an end result, the processing pipeline comprising a plurality of processing circuits, each configured to perform an operation to provide a result during at least one stage of the plurality of stages, wherein the plurality of processing circuits comprises a plurality of multiplier circuits, each configured to produce a multiplication result during at least one stage of the plurality of stages, wherein the plurality of multiplier circuits comprises a first multiplier circuit and a second multiplier circuit that are configured to operate in parallel, such that at a same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform processing, wherein the plurality of multiplier circuits comprises a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, wherein the third multiplier circuit is configured to process outputs from the first multiplier circuit and the second multiplier circuit, wherein at least one of the plurality of multiplier circuits is configured to, during evaluation by the processing pipeline of the first mathematical function: perform processing during a first time period; and perform processing during a second time period following the first time period, wherein control circuitry of the hardware module is configured to: following a start of the first time period, and during evaluation by the processing pipeline of the first mathematical function, configure a supply of values to the at least one of the plurality of multiplier circuits for performing processing during the second time period.
 2. The execution unit of claim 1, wherein the execution unit is configured to: execute an instruction comprising an op code indicating the first mathematical function; and provide control information associated with the instruction to the control circuitry to cause the control circuitry to control a supply of values to the plurality of processing circuits so as to cause the processing pipeline to evaluate the first mathematical function with respect to an operand defined by the instruction.
 3. The execution unit of claim 2, wherein the execution unit is further configured to: in response to the execution of the instruction, provide a first at least one input value dependent upon the operand to the processing pipeline, wherein the first at least one input value comprises the operand.
 4. The execution unit of claim 1, wherein the first time period is a first time slot belonging to a plurality of time slots and the second time period is a second time slot belonging to the plurality of time slots, wherein the processing pipeline is configured to, for each of the plurality of stages, assign one of the plurality of time slots for performing processing associated with the respective stage for evaluating the first mathematical function.
 5. The execution unit of claim 1, wherein the at least one of the plurality of multiplier circuits is configured to: perform processing associated with the first mathematical function during the first time period; and perform processing associated with a second mathematical function during the second time period.
 6. The execution unit of claim 1, wherein the control circuitry comprises a plurality of multiplexers of the processing pipeline configured to control which values are provided to each of the plurality of processing circuits.
 7. The execution unit of claim 1, wherein the outputs from the first multiplier circuit and the second multiplier circuit are modified by further processing circuitry of the plurality of processing circuits prior to being provided to the third multiplier circuit for processing.
 8. The execution unit of claim 1, wherein the plurality of processing circuits comprise one or more items selected from the list consisting of: at least one addition circuit configured to determine an addition result; at least one subtraction circuit configured to determine a subtraction result; and a circuit configured output a result from a look up table.
 9. The execution unit of claim 1, wherein the first mathematical function comprises an item selected from the list consisting of: an exponential function; a divide function; a square root function; and a logarithm function.
 10. The execution unit of claim 1, wherein the execution unit is configured to, when evaluating the first mathematical function: process, in the pipeline, one or more input values to produce one or more output values; supply at least one of the one or more output values as at least one input to a start of the processing pipeline; and process, in the pipeline, the at least one of the one or more output values to produce a result for the first mathematical function.
 11. A method of operating an execution unit in a processor, the execution unit comprising a hardware module having a processing pipeline configured to perform calculations to evaluate a first mathematical function, wherein the processing pipeline comprises a plurality of stages through which the calculations for evaluating the first mathematical function progress to an end result, the method comprising: performing, in the processing pipeline, an operation to provide a result during at least one stage of the plurality of stages, wherein the processing pipeline includes a plurality of multiplier circuits; operating a first multiplier circuit of the plurality of multiplier circuits and a second multiplier circuit of the plurality of multiplier circuits in parallel such that at a same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform processing; processing, at a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, outputs from the first multiplier circuit and the second multiplier circuit; performing, by at least one of the plurality of multiplier circuits, processing during a first time period; performing, by the at least one of the plurality of multiplier circuits, processing during a second time period following the first time period; following a start of the first time period, and during evaluation by the processing pipeline of the first mathematical function, configuring a supply of values to the at least one of the plurality of multiplier circuits for performing processing during the second time period.
 12. The method of claim 11, the method further comprising: controlling a supply of values to the plurality of multiplier circuits to cause the processing pipeline to evaluate the first mathematical function with respect to an operand defined by an instruction.
 13. The method of claim 11, wherein the first time period is a first time slot belonging to a plurality of time slots and the second time period is a second time slot belonging to the plurality of time slots, wherein the processing pipeline is configured to, for each of the plurality of stages, assign one of the plurality of time slots for performing processing associated with the respective stage for evaluating the first mathematical function.
 14. The method of claim 11, wherein the at least one of the plurality of multiplier circuits is configured to: perform processing associated with the first mathematical function during the first time period; and perform processing associated with a second mathematical function during the second time period.
 15. The method of claim 11, further comprising, when evaluating the first mathematical function: processing, in the pipeline, one or more input values to produce one or more output values; supplying at least one of the one or more output values as at least one input to a start of the processing pipeline; and processing, in the pipeline, the at least one of the one or more output values to produce a result for the first mathematical function.
 16. An execution unit for a processor, the execution unit comprising a hardware module having a processing pipeline configured to perform calculations to evaluate a first mathematical function, the execution unit comprising a plurality of multiplier circuits comprising: a first multiplier circuit and a second multiplier circuit arranged in parallel, such that at a first stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit produce multiplication results at the first stage; and a third multiplier circuit arranged in series with the first multiplier circuit and the second multiplier circuit, wherein the third multiplier circuit is configured to multiply the multiplication results from the first multiplier circuit and the second multiplier circuit, wherein at least one of the plurality of multiplier circuits is configured to, during evaluation by the processing pipeline of the first mathematical function: perform processing during a first time period; and perform processing during a second time period following the first time period, and wherein control circuitry of the hardware module is configured to: following a start of the first time period, and during evaluation by the processing pipeline of the first mathematical function, configure a supply of values to the at least one of the plurality of multiplier circuits for performing processing during the second time period.
 17. The execution unit of claim 16, wherein the control circuitry is configured to: execute an instruction comprising an op code indicating the first mathematical function; and provide control information associated with the instruction to the control circuitry to cause the control circuitry to control the supply of values so as to cause the processing pipeline to evaluate the first mathematical function with respect to an operand defined by the instruction.
 18. The execution unit of claim 16, wherein the first time period is a first time slot belonging to a plurality of time slots and the second time period is a second time slot belonging to the plurality of time slots, wherein the processing pipeline is configured to, for each of the plurality of multiplier circuits, assign at least one of the plurality of time slots for performing processing for evaluating the first mathematical function.
 19. The execution unit of claim 16, wherein the at least one of the plurality of multiplier circuits is configured to: perform processing associated with the first mathematical function during the first time period; and perform processing associated with a second mathematical function during the second time period.
 20. The execution unit of claim 16, wherein the execution unit is configured to, when evaluating the first mathematical function: process, in the pipeline, one or more input values to produce one or more output values; supply at least one of the one or more output values as at least one input to a start of the processing pipeline; and process, in the pipeline, the at least one of the one or more output values to produce a result for the first mathematical function. 